This application relates to
1. U.S. patent application Ser. No. 09/552,285 entitled xe2x80x9cRedundancy Scheme to Improve Programming Yield for Non-Volatile Memory Using Gate Breakdown Structure in Standard Sub 0.25 Micron CMOS Processxe2x80x9d commonly owned and filed concurrently with the present application.
2. U.S. patent application Ser. No. 09/552,625 entitled xe2x80x9cImproved Array Arrangement for Non-Volatile Memory Using Gate Breakdown Structure in Standard Sub 0.25 Micron CMOS Processxe2x80x9d commonly owned and filed concurrently with the present application.
3. U.S. patent application Ser. No. 09/524,971 entitled xe2x80x9cIntellectual Property Protection in a Programmable Logic Devicexe2x80x9d commonly owned and filed Mar. 14, 2000. These related applications are incorporated herein by reference.
This invention relates to integrated circuits, and more particularly to memory architectures including various cell structures and charge pumps for use in non-volatile memory arrays.
Many integrated circuits now in use are fabricated in what is called CMOS (complimentary metal oxide semiconductor) technology, which forms both PMOS and NMOS transistors in a semiconductor substrate. The term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductor material, including, but not limited to, bulk semiconductor materials such as a semiconductor wafer (either alone or in assemblies comprising other material they are on), and semiconductor material layers (either alone or in assemblies comprising other materials). The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
One of the main objectives of integrated circuit technology is to minimize transistor size. Typically, transistors are described in terms of their minimum feature dimension. Current technology provides a minimum feature size of 0.35 micron or less. The minimum feature size, which is also referred to as a xe2x80x9cline widthxe2x80x9d, refers to the minimum width of a transistor feature such as the gate width, or the separation between source and drain diffusion regions. Typically, 0.35-micron technology is used to form CMOS transistors having gate oxide thicknesses of around 70 Angstrom. A 0.18-micron technology is used to form CMOS transistors having a gate oxide thickness of around 35-40 Angstrom. A 0.15-micron technology is used to form CMOS transistors having a gate oxide thickness of around 25-30 Angstrom. The gate xe2x80x9coxidexe2x80x9d is typically an oxide dielectric layer that is interposed between the conducting gate electrode, which is typically a polycrystalline silicon structure formed overlying the principle surface of a substrate in which the integrated circuit is formed, and the underlying substrate which typically is the channel portion of the transistor extending between the source and the drain regions. Transistors formed using the 0.35-micron technology typically operate at a voltage of 3.3 Volts. Transistors formed using the 0.18-micron technology typically operate at a voltage of 1.8 Volts. Greater voltages are likely to destroy the transistor by rupturing the gate oxide.
In the field of data storage, there are two main types of storage elements. The first type of storage element is a volatile storage element such as typically used in DRAM (dynamic random access memory) or SRAM (static random access memory) in which the information stored in a particular storage element is lost when power is removed from the circuit. The second type of storage element is a non-volatile storage element in which the information is preserved even if power is removed. Typically, the types of elements used to provide non-volatile storage are substantially different from those used in ordinary logic circuitry or in volatile storage, thereby requiring different fabrication techniques. It has heretofore not been possible to include non-volatile storage on an integrated circuit chip formed exclusively using standard CMOS processes.
Memory architectures including various cell structures for use in non-volatile memory arrays and methods of programming memory cells are described. In the described embodiments, the cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures are fabricated using 0.18 micron or 0.15 micron standard CMOS processes. This enables the transistors that are utilized for both the storage transistors and the pass transistors (I/O transistors) to be formed using standard CMOS processing techniques.
Advantageously, the cell structures that are formed can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.
In particular embodiments, the cell structures are fabricated utilizing standard 0.18 micron or 0.15 micron CMOS processes. In these embodiments, memory cells are fabricated comprising storage structures, including transistors, having different gate breakdown characteristics, e.g. as impacted by the thicknesses of their gate dielectric layers. The memory cells are programmed by taking advantage of the different gate breakdown characteristics of the different memory cells.
In one embodiment, a method of programming a non-volatile memory cell comprises providing a storage transistor over a substrate. The storage transistor comprises a gate and a pair of source/drain regions that are formed within the substrate. A programming voltage is applied to the storage transistor sufficient to form a conductive path between the gate and one of the pair of source/drain regions.
In another embodiment, a method of programming a non-volatile memory cell comprises providing a storage structure over a substrate. The storage structure comprises a gate at least a portion of which is disposed proximate a region of the substrate. The gate and the substrate region comprise the same type material. A programming voltage is applied to the storage structure sufficient to form a conductive path between the gate and the substrate region.
In yet another embodiment, a non-volatile memory cell comprises a substrate and a low voltage CMOS storage transistor supported by the substrate. The storage transistor comprises a gate, a gate dielectric, and a pair of source/drain regions received within the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor having a pair of source/drain regions. One of the pair of source/drain regions of the p-channel transistor is coupled with one of the pair of source/drain regions of the CMOS storage transistor. The storage transistor is configured for programming through the p-channel transistor.
In yet another embodiment, a non-volatile memory cell comprises a substrate and a low voltage p-channel storage transistor supported by the substrate. The storage transistor comprises a gate, a gate dielectric, and a pair of source/drain regions received within a well in the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor having a pair of source/drain regions. One of the pair of source/drain regions of the high voltage p-channel transistor is coupled with the gate of the low voltage p-channel storage transistor. The storage transistor is configured for programming through the high voltage p-channel transistor. In a further embodiment, a field programmable gate array (FPGA) comprises a substrate, a plurality of word lines supported by the substrate, a plurality of bit lines supported by the substrate, and a plurality of memory cells supported by the substrate. Each memory cell comprises a low voltage CMOS storage transistor that comprises a gate, a gate dielectric, and a pair of source/drain regions received within the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor having a gate and a pair of source/drain regions. One of the pair of source/drain regions of the p-channel transistor is coupled with one of the pair of source/drain regions of the CMOS storage transistor. The other of the pair of source/drain regions of the p-channel transistor is coupled with one of the plurality of bit lines. The gate of the p-channel transistor is coupled with one of the plurality of word lines. The storage transistor is configured for programming through the p-channel transistor.
In another embodiment, a field programmable gate array (FPGA) comprises a substrate, a plurality of word lines supported by the substrate, a plurality of bit lines supported by the substrate, and a plurality of memory cells supported by the substrate. Each memory cell comprises a low voltage p-channel storage transistor that comprises a gate, a gate dielectric, and a pair of source/drain regions received within a well in the substrate. The memory cell is configured for programming by rupturing the gate dielectric of the storage transistor. The memory cell also comprises a high voltage p-channel transistor comprising a gate and a pair of source/drain regions. One of the pair of source/drain regions of the high voltage p-channel transistor is coupled with the gate of the low voltage p-channel storage transistor. The other of the pair of source/drain regions of the high voltage p-channel transistor is coupled to one of the plurality of bit lines. The gate of the high voltage p-channel transistor is coupled to one of the plurality of word lines and the storage transistor is configured for programming through the high voltage p-channel transistor.
In still a further embodiment, a field programmable gate array (FPGA) comprises a substrate, a plurality of word lines supported by the substrate, a plurality of bit lines supported by the substrate, and a plurality of memory cells supported by the substrate. Each memory cell comprises a gate, a substrate region, and a dielectric material disposed between the gate and the substrate region. The gate is disposed over the substrate region, and both the gate and the substrate region comprise the same type material. The dielectric material is configured to breakdown in the presence of a specific programming configuration so that a conductive path is formed between the gate and the substrate region thereby programming the memory cell.
In other embodiments, charge pumps are fabricated using the same standard CMOS processing techniques that are used to form the memory cells. This advantageously enables an on-chip charge pump to provide the necessary programming voltage and current so that the cell can be programmed.
In one charge pump embodiment, a charge pump comprises a semiconductor substrate, a plurality of diodes supported by the substrate, and a plurality of high voltage CMOS transistors each of which having source/drain regions and a gate. The diodes are connected to form a path between a voltage supply node and a programming voltage node. The source/drain regions of at least some of the transistors are commonly coupled at different locations along the path defined by the diodes. At least some of the gates are individually coupled to one of two clock signal lines. In one aspect, the charge pump comprises a portion of a non-volatile memory device that includes a non-volatile memory array programming by the programming voltage that is developed by the charge pump.
In another charge pump embodiment, a charge pump circuit comprises a semiconductor substrate, a pair of clock signal lines supported by the substrate, a plurality of diodes supported by the substrate, a first plurality of p-channel transistors each of which having source/drain regions and a gate, and a second plurality of p-channel transistors each of which having source/drain regions and a gate. The diodes are connected to form a path between a voltage supply node and a programming voltage node that provides a programming voltage. The source/drain regions of the first plurality of transistors are commonly coupled at different locations along the path defined by the diodes, and the gates are coupled to one of the pair of clock signal lines. The source/drain regions of the second plurality of transistors are commonly coupled at different other locations along the path defined by the diodes, and the gates are coupled to the other of the pair of clock signal lines.